Market Context — Why This Technology, Why Now

The global push for more intelligent and autonomous systems, from smart factories to advanced consumer electronics, necessitates highly efficient on-device AI processing. As AI models grow in complexity, the demand for flexible, power-optimized computational cores intensifies. This technology aligns with industry trends towards smaller, more powerful, and energy-efficient edge devices, offering a strategic advantage in a competitive landscape driven by performance-per-watt metrics and the need to reduce carbon footprint in computing infrastructure.

Key Competitive Advantages
01

Reduces circuit footprint by up to ~30% by flexibly partitioning and reconfiguring multipliers and adders based on operational precision modes.

02

Achieves highly efficient multiplication for various precision levels through optimal unit allocation and connection switching based on the selected operation precision mode.

03

Dynamically adjusts computational resources according to required precision, suppressing unnecessary power consumption and significantly contributing to energy efficiency.

Market Opportunity
Edge AI Processors
$8B–$12B globally (AI est.)
In the edge AI market, where real-time inference and low power consumption are critical, this technology provides a high-performance, power-efficient computing foundation, enhancing market competitiveness.
Edge AI chip manufacturers Autonomous driving SoC developers Industrial IoT hardware providers
Embedded Systems
$4B–$7B globally (AI est.)
For embedded systems in industrial and medical equipment requiring efficient processing of diverse sensor data, this technology contributes to improved computational efficiency and miniaturization.
Industrial control system developers Medical device manufacturers Consumer electronics OEMs
Data Center Accelerators
$10B–$15B globally (AI est.)
In cloud AI and big data analytics, power efficiency and throughput of computing accelerators are crucial, and this technology has the potential to meet these demands.
Cloud service providers AI accelerator card developers High-performance computing vendors
IP Defensibility — Why Competitors Can't Replicate This
What This Patent Covers

This patent protects the core logic of a computing device, specifically its variable precision multiplication capabilities, through 11 robust claims. It successfully navigated a rigorous examination process, including two rejections and citations of two prior art documents, demonstrating strong patentability and clear, stable claim scope. This robust IP foundation minimizes invalidation risks, providing licensees with confidence for secure business expansion.

Competitive White Space

This patent primarily covers the core arithmetic unit design. Licensees could explore building additional IP around novel system-on-chip (SoC) architectures for specific AI workloads, advanced memory management units, or specialized compilers that optimize code for this variable precision hardware.

Economic Impact
~$200K/year estimated cost reduction per facility (est.)
estimated ROI · USD · AI analysis
ROI Calculation Logic

Assuming a 20% reduction in circuit size compared to conventional methods, the manufacturing cost per semiconductor chip could be reduced by ~$2.00 (AI est.). For an annual production of 100,000 units, this could result in an estimated annual manufacturing cost reduction of ~$200K (AI est.). Additionally, optimized power consumption may reduce operational electricity costs in data centers and edge devices.

Speed to Market
6× faster than in-house development
This technology is a patent related to the core logic of a computing device, with clearly defined algorithms and circuit configurations. This eliminates the need for licensees to conduct research and development from scratch, allowing for significant reductions in design and verification periods by integrating it into existing LSI design flows. The detailed circuit configuration disclosed in the patent specification, coupled with low technical uncertainty, enables rapid implementation and market entry.
Competitive Positioning

X: Computational Efficiency & Power Saving
Y: Circuit Footprint Optimization

Business Models & Applications
🤝 IP Licensing Model
Licensing this technology as an IP core to semiconductor manufacturers and SoC development companies to promote its adoption across a wide range of products, generating royalty revenue.
💡 Custom SoC/FPGA Development Services
Undertaking the development of custom SoCs or FPGAs incorporating this technology, providing high-performance computing solutions optimized for specific customer requirements.
☁️ Cloud AI Computing Platform
Applying this technology to computing accelerators in data centers to offer low-latency, high-efficiency AI computing services via the cloud.
Adjacent Application Opportunities
🚗 Autonomous Driving
Real-time Image Processing Engine for Autonomous Driving
This technology could be utilized as a dedicated processing engine for efficiently handling large volumes of real-time sensor data from LiDAR and cameras in autonomous driving systems with variable precision. It could achieve both low latency and power efficiency, contributing to a significant boost in in-vehicle AI performance.
⚙️ Industrial Robotics
High-Efficiency Motion Control Processor for Industrial Robotics
Applicable to processors for precise motion control in industrial robots and high-speed integration of multiple sensor inputs (e.g., vision, tactile). Variable precision computing could optimize processing load based on situational needs, enhancing responsiveness and energy efficiency by an estimated ~20%.
🏥 Medical Devices
Data Analysis for Portable Medical Diagnostic Devices
Could serve as a core technology for high-efficiency analysis of biological and image data in portable medical diagnostic devices, where miniaturization and lightweight design are crucial. It has the potential to extend battery life by up to ~30% and improve diagnostic accuracy, fostering new medical services.
Integration Roadmap — Estimated 18-Month Deployment
Phase 1: Technology Evaluation & Design
Duration: 3 months
Evaluates the technology's suitability for existing products and development roadmaps, then defines specific implementation requirements and architectural design.
Phase 2: Prototype Development & Verification
Duration: 6 months
Develops an FPGA-based prototype incorporating this technology and verifies its performance and power consumption under actual application environments.
Phase 3: Productization & Mass Production Preparation
Duration: 9 months
Based on prototype verification results, proceeds with ASIC design or SoC integration, conducting final optimization and reliability evaluation for mass production.
Technical Feasibility
This technology is highly compatible with existing digital circuit design techniques and can be easily implemented using standard hardware description languages such as Verilog-HDL or VHDL. The logic for dividing and reconfiguring multipliers and adders, as described in the claims, can be integrated into existing SoC development processes without significant new capital investment, by combining it with existing semiconductor IP and design tools. This implies low technical hurdles and anticipates early implementation.
Success Scenario
Implementing this technology could improve the computational processing efficiency of edge AI devices by up to 25%. This may extend battery life and enable more complex AI models to run on smaller devices, significantly enhancing market competitiveness. It could also increase product design flexibility, potentially opening new application areas.
Patent Record
APPLICATION NO.
特願2020-509352
REGISTRATION NO.
7394462
FILING DATE
2019/03/29
GRANT DATE
2023/11/30
EXPIRATION DATE
2039/03/29
PATENT HOLDER
国立研究開発法人理化学研究所
Examination History
2021年12月16日
出願審査請求書
2022年12月13日
拒絶理由通知書
2023年04月03日
意見書
2023年04月03日
手続補正書（自発・内容）
2023年07月04日
拒絶理由通知書
2023年08月09日
意見書
2023年08月09日
手続補正書（自発・内容）
2023年10月24日
特許査定